Intel CEO Pat Gelsinger's new ironclad rule: Employees will be fired if a chip design fails mass production after two tape-outs

According to a report by foreign media Tom's Hardware on the 20th local time, Intel CEO Pat Gelsinger is making major adjustments to Intel's internal chip development culture. One of the core requirements is that the A0 version of a chip, after its initial tape-out, must be capable of direct mass production.

Previous reports indicated that Gelsinger would personally review chip designs and approve tape-outs. More recently revealed internal requirements show that Gelsinger not only expects design teams to reduce defects but also hopes chips in the A0 stage can reach near-production maturity—not relying on successive revisions to fix problems, as was done in the past.

At the recent JPMorgan Global Technology, Media & Communications Conference, Gelsinger said: "I'm now establishing a new culture. The A0 version must be able to go directly into mass production. Intel never had this culture before, so now I require A0 to pass in one go. If you get to B0, you can still keep your job, but after that, you're fired."

Gelsinger further explained that at first, many employees thought these requirements were a joke, but as the system actually rolled out, people within Intel have realized the management standards are changing. Currently, Intel strictly checks all designs, defect fixes, and the IP modules to be used before tape-out, making sure all verification is complete before formal tape-out is allowed.

IT HomeNote:A0 is the first hardware version after a chip’s initial tape-out. A successful A0 means the chip can start up, function normally, meet major specification requirements, and is close to mass-production quality, all without significant modifications.

However, this is an especially challenging target for large CPUs using advanced processes. In contrast, some processors with simpler structures and more redundancy in the design are easier to achieve successful tape-out on the first try.

Previously, Intel typically required several rounds of stepping versions to resolve defects, optimize performance, and improve yields. For example, the Intel Xeon Sapphire Rapids server processor was reportedly found to have about 500 defects. To fix these issues and reach expected performance and yield targets, Intel successively launched multiple steppings, including A0, A1, B0, C0, C1, C2, D0, E0, E2, E3, E4, and E5.